Modern integrated circuits ("ICs") are composed of up to several million individual electronic devices, such as transistors and capacitors, fabricated on and near the surface of a single-crystal wafer of a semiconductor material, such as silicon. Such devices are composed of features, such as regions having specific electrical properties, of less than one micron in size. Minute crystal imperfections and contamination, such as metals unintentionally introduced into the semiconductor during manufacturing processes, can change the electrical properties of the devices and adversely affect their performance.
It has been impossible to prevent the introduction of metallic contamination into the semiconductor wafers upon which integrated circuits are fabricated. IC manufacturers have, therefore, developed methods for trapping, or "gettering," the inevitable metallic contamination at locations away from the surface layer at which the electronic devices are fabricated.
One type of gettering, known as internal or intrinsic gettering, entails creating microdefects in the crystal structure of the silicon wafer. Microdefects such as dislocations and oxide precipitates are created in the bulk region of semiconductor silicon wafers, away from the surface region where the electronic devices are formed. Metallic contamination, which is randomly diffusing throughout the substrate, becomes trapped in the microdefects away from the electronic devices.
Internal gettering results in better device performance and increased yield, i.e., the number of good dies per wafer. The microdefects, however, must be formed only in regions away from the wafer surface, because an electronic device fabricated on a microdefect would not function as designed. Silicon wafers are processed, therefore, to create a bulk region in which microdefects are formed and a microdefect-free layer near the surface where the devices are to be fabricated. An optimized IC manufacturing process produces a well-defined microdefect-free layer in which the IC devices are fabricated.
Microdefects within a semiconductor silicon crystal are typically formed by precipitating oxides within the silicon as described in, for example, Andrews, "Oxygen Out-Diffusion Model for Denuded Zone Formation in Czochralski-Grown Silicon with High Interstitial Oxygen Contents" Proceedings of the Symposium on Defects in Silicon (1983). To provide oxygen for forming the oxides, a crystal ingot is typically grown with between 10 ppma and 50 ppma interstitial oxygen (All oxygen concentrations recited in this document are described with reference to the "Old ASTM" standard.) The oxygen typically enters the molten silicon from a quartz crucible used to hold the molten silicon during the crystal growing process. As the ingot cools in the growing furnace, oxide precipitation nuclei form therein.
The ingot is sliced into wafers, which, after several known preparatory steps, are polished to prepare their surfaces for integrated circuit fabrication. The wafers are then heated to a high temperature, typically between 1,100.degree. and 1,200.degree. C., to outdiffuse or drive off oxygen near their surfaces and thereby dissolve the oxide precipitate nuclei created as the crystal cooled in the growing furnace. The wafers are subsequently heated for several hours at a lower temperature, typically between 600.degree. C. and 800.degree. C., to nucleate oxide microdefects away from the surface. A third heating step at a temperature of between 900.degree. C. and 1,200.degree. C. for several hours grows or enlarges the microdefects.
Because the first, high temperature heating step drives away oxygen and dissolves the defect nuclei in a layer near the wafer surface, the oxide microdefects cannot form in that layer during the subsequent nucleation step, and the layer near the surface remains free of microdefects. The change in oxygen concentration from the bulk to the surface after the high temperature out-diffusion step is relatively shallow, so it is difficult to accurately determine at what distance below the wafer surface the oxygen concentration will be great enough to form microdefects. The shallow concentration gradient of the dissolved oxygen produces a relatively shallow concentration gradient of the microdefects from a high concentration in the bulk to substantially zero in the microdefect-free layer. This gradual change in microdefect density makes detecting the beginning of the microdefect-free layer difficult.
There are several methods for measuring the depth of the microdefect-free layer. One common method entails heat treating, cleaving, and then lapping the silicon wafer at a small angle, typically 1.degree. to 2.degree.. The wafer is then etched in a preferential etch solution, such as a known Wright, Secco, or Sirtle etch solution, to reveal the microdefects and oxide precipitates. The depth of the microdefect-free layer is then determined by manually measuring under an optical microscope the distance from the wafer surface to the etch pits corresponding to the microdefects. The depth of the microdefect-free layer can also be measured using automated equipment such as a light scattering tomograph, in which the light scattered from microdefects and oxide precipitates is detected. Other methods used to measure the thickness of the microdefect-free layer include an x-ray diffraction microscope, a differential interference contrast microscope, and a transmission electron microscope.
The accuracy of automated measurements methods depends on the size of the microdefects and on the background noise level from the optical and electronic components. It has been very difficult to obtain accurate measurements of microdefect-free layers because the variation in microdefect-free layer depth in the calibration wafers makes it virtually impossible to characterize the equipment noise so that its effect can be removed from subsequent measurements.
The inability to accurately measure the depth of microdefect layers has made it difficult to control the processes that form the microdefect layer, thereby reducing the quality and consistency of the semiconductor substrates used in integrated circuit fabrication.